System Design in VHDL

Today's digital systems are rapidly reaching an extent whose complexity is not easy to understand. Therefore, the system designer needs special tools which allow him to keep track of the entire system as well as to be able to work on details precisely.

A great help here is the hardware description language VHDL. VHDL stands for "VHSIC Description Language", whereby VHSIC means "Very High Speed Integrated Circuit". It makes it possible to first describe the behavior of a system on an abstract level and then refine individual areas bit by bit until the description can actually be realized as hardware.

When working with VHDL, the following tools are available at the IKR:

Graphical VHDL input

A graphical input tool simplifies many steps of VHDL input and debugging with

  • Outline of the design in individual blocks
  • Graphical input of state machines
  • Flow charts
  • Tabular logic definitions

At the IKR as input tool "Renoir" of Mentor Graphics is used.

It is used for

  • implementation of bachelor and master theses
  • in the practical course "Rechnerarchitektur".

VHDL simulator

A designed system must be tested at every design pase to locate and correct errors. A simulator must therefore be able to display the designed system in a variety of ways:

  • structure-tree-representation
  • waveforms
  • value lists
  • variable contents
  • current position within the source code
  • interaction with the input tool

At the IKR as VHDL simulator "Modelsim" of Mentor Graphics is used.

It is used for

  • implementation of bachelor and master theses
  • in the practical course "Rechnerarchitektur" and
  • at the excercises of the lecture "Entwurf Digitaler Systeme"

Synthesis with VHDL

A VHDL system tool generates from the VHDL description a data format that allows the mapping of the logic to the corresponding target technology. In addition, the time constraints must be taken into account and their compliance be checked. If this is not possible, the developer needs tools to optimize time-critical data paths. A synthesis tool therefore has:

  • logic optimization
  • Graphical representations of
    • Read VHDL code
    • Illustration on the target technology
    • (Time) critical data paths
  •  
  • Analysis of the result of the synthesis

At the IKR as tool for synthesis "Renoir" of Mentor Graphics is used.

It is used for

  • implementation of bachelor and master theses
  • in the practical course "Rechnerarchitektur".

Contact Us

 

Institute of Communication Networks and Computer Engineering

Pfaffenwaldring 47, 70569 Stuttgart

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