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Institute of Communication Networks and Computer Engineering (IKR)

Homepage of Dipl.-Ing. Matthias Meyer

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Dipl.-Ing. Matthias Meyer

Research Group Leader

Phone

+49-(0)711-685-67975

Fax

+49-(0)711-685-67983

Room

1.334

E-Mail

Matthias Meyer

Address

University of Stuttgart, IKR
Pfaffenwaldring 47
D 70569 Stuttgart
Germany


 Activities 

 Publications 

2010

Horvath, O.; Meyer, M.
Fine-Grained Parallel Compacting Garbage Collection through Hardware-Supported Synchronization
5th International Symposium on Embedded Multicore SoCs, San Diego, 2010
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Meyer, M.
Prozessorarchitektur für exakte Zeigeridentifizierung
Patent, No EP 1 639 475 B1, September 2010
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2007

Stanchina, S.; Meyer, M.
Mark-Sweep or Copying? A 'Best of Both Worlds' Algorithm and a Hardware-Supported Real-Time Implementation
Proceedings of the 2007 International Symposium on Memory Management, Montreal, October 2007
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Stanchina, S.; Meyer, M.
Exploiting the Efficiency of Generational Algorithms for Hardware-Supported Real-Time Garbage Collection
Proceedings of the 22nd ACM Symposium on Applied Computing, SAC 2007, Seoul, March 2007
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2006

Meyer, M.
A True Hardware Read Barrier
Proceedings of the 2006 International Symposium on Memory Management, Ottawa, Ontario, June 2006, pp. 3-16
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2005

Meyer, M.
An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems
Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Hong Kong, August 2005, pp. 517-524
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2004

Meyer, M.
A Novel Processor Architecture with Exact Tag-Free Pointers
IEEE Micro, Vol. 24, No. 3, May 2004, pp. 46-55
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2003

Meyer, M.
A Novel Processor Architecture with Exact Tag-Free Pointers
Proceedings of the 2nd Workshop on Application Specific Processors, San Diego, California, December 2003, pp. 96-103
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