The steeply rising usage of the Internet for multimedia applications requires large and scalable router architectures to handle the exploding amounts of traffic. This paper presents a novel system architecture for packet switches and routers with Ethernet interfaces. It consists of packet protocol processing chips with more than 20 Ethernet/Fast-Ethernet/ Gigabit-Ethernet interfaces and central crossbar-based switching chips used for interconnecting these protocol chips. While each crossbar switching chip alone provides a throughput of nearly 100 Gbps the crossbar switching chips themselves can also be cascaded in ring structures allowing a total system throughput in the order of several hundred Gbps. The overall architecture operates in a virtual output queuing mode supported by a sophisticated internal messaging.
Year
2001
Reference entry
Kirstädter, A.; Heink, M.; Fiedler, U.; Heer, C. A Highly Scalable Switching and Routing Chipset
Proceedings of the World Multiconference on Systemics, Cybernetics and Informatics, ISAS-SCIs 2001, Orlando, FL, July 2001